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1. Field of the Invention
Aspects of the invention relate to methods for receiving information over a parallel data bus structure. Other aspects of the invention relate to apparatuses for receiving information over a parallel bus structure.
2. Description of Background Information
As channel data rates are increased, timing skew of data paths relative to the clock limits the ability to correctly receive synchronous data. For example, the maximum timing skew in a Small Computer Standard Interface (SCSI) Ultra-3 system with a 12.5 ns bit-cell time is xc2x13.75 ns. The next generation SCSI, Ultra-4, is planned to operate with similar interconnect structures, but with a bit-cell time of 6.25 ns. The uncorrected 7.5 ns peak-peak skew, of the Ultra-4, exceeds the bit-cell time, thereby preventing correct data reception.
An embodiment of the invention provides a method of performing timing de-skew in order to properly receive digital computer information. N sequences of clock pulses are generated, the generated sequences having phases offset from one another by intervals of T/N, where N is at least 2 and T is a duration of one bit-cell time, and where one cycle of each of the sequences has a duration of 2T. A transmitting portion generates a test signal. The test signal is received at a receiving potion. An identifying portion identifies which one of the generated sequences of clock pulses and corresponding polarities is aligned with the test signal. The identified one of the generated sequences of clock pulses and the corresponding polarities are used to determine which one of the generated sequences of clock pulses and corresponding polarities to use to receive the digital computer information.